CD4071BF

CD4071BF Manufacturer

CD4071BF Description

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CD4071BF Datasheet (PDF)

CD4071BF Price & Availability

CD4071BF Features

• Medium-Speed Operation - t_PLH, t_PHL= 60 ns (typ.) at V_DD= 10 V
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Standardized, symmetrical output characteristics
• Noise margin (full package-temperature range):
  
  1 V at V_DD= 5 V
  
  2 V at V_DD= 10 V
  
  2.5 V at V_DD= 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ?B? Series CMOS Devices"

CD4071BF Parameters

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