| CD4085B Description |
| CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate |
| CD4085B Vendor |
| Texas Instruments |
| CD4085B Categories |
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| CD4085B Features |
- Medium-speed operation - tPHL= 90 ns; tPLH= 125 ns (typ.) at 10 V
- Individual inhibit controls
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (over full package-temperature range):
- 1 V at VDD= 5 V
- 2 V at VDD= 10 V
- 2.5 V at VDD= 15 V
- 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
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| CD4085B Datasheet and Application Notes |
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| Parameter | Value |
| Voltage Nodes (V) | 5, 10, 15 |
| Products related to CD4085B |
CD4085BF CD4085BNSR CD4085BM96 CD4085BM
CD4085BPWR CD4085BE CD4085BPW CD4085BMT
CD4085BF3A |