CD4085BPW

CD4085BPW Manufacturer

CD4085BPW Description

CD4085BPW Description

CD4085BPW Categories

CD4085BPW Datasheet (PDF)

CD4085BPW Price & Availability

CD4085BPW Features

• Medium-speed operation - t_PHL= 90 ns; t_PLH= 125 ns (typ.) at 10 V
• Individual inhibit controls
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (over full package-temperature range):
  • 1 V at V_DD= 5 V
  • 2 V at V_DD= 10 V
  • 2.5 V at V_DD= 15 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4085BPW Parameters

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