| CD4508BPW Description | | CMOS Dual 4-Bit Latch | | CD4508BPW Vendor | | Texas Instruments | | CD4508BPW Features | - Two independent 4-bit latches
- Individual master reset for each 4-bit latch
- 3-state outputs with high-impedance state for bus line applications
- Medium-speed operation: tPHL= tPLH= 70 ns (typ.) at VDD= 10 V and CL= 50 pF
- 100% tested for quiescent current at 20 V
- 5-V, 10-V, and 15-V parametric ratings
- Standardized, symmetrical output characteristics
- Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
- Noise margin (full package-temperature range) =
1 V at VDD= 5 V
2 V at VDD= 10 V
2.5 V at VDD= 15 V - Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
- Applications:
- Buffer storage
- Holding registers
- Data storage and multiplexing
| | CD4508BPW Datasheet and Application Notes | | | Parameter | Value | | Voltage Nodes (V) | 5, 10, 15 | | Status | ACTIVE | | Temp (oC) | -55 to 125 | | Budget Price ($US) | QTY | 1.36 | 1KU | | Package Type| Pins | TSSOP (PW) | 24 | | STD Pack QTY | 60 | | Products related to CD4508BPW | CD4508BPWR CD4508BM CD4508BF3A CD4508B
CD4508BNSR CD4508BM96 CD4508BD3 CD4508BE
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