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CD4517B

CD4517B Description

CD4517B Categories

CD4517B Manufacturer

CD4517B Datasheet (PDF)

CD4517B Datasheet
CMOS Dual 64-Stage Static Shift Register

CD4517B Price & Availability


Check CD4517B Price & Availability at Canics

CD4517B Features

  • Low quiescent current - 10 nA/pkg (typ.) at VDD= 5 V
  • Clock frequency 12 MHz (typ.) at VDD= 10 V
  • Schmitt trigger clock inputs allow operation with very slow clock rise and fall times
  • Capable of driving two low-power TTL loads, one low-power Schottky TTL load, or two HTL loads
  • Three-state outputs
  • 100% tested for quiescent current at 20 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
  • Applications:

    Time-delay circuits

    Scratch-pad memories

    General-purpose serial shift-register applications

CD4517B Parameters

Voltage Nodes (V)5, 10, 15
Select parameters and click to see components with these parameters.

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Keywords
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