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CD4572UBPW Datasheet (PDF)
CD4572UBPW Price & Availability
CD4572UBPW Features- Pin 7 NOR input positioned adjacent to VSSfor easy use of gate as an inverter
- Pin 15 NAND input positioned adjacent to VDDfor easy use of gate as an inverter
- Standard symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 18 V over full package-temperature range:
100 nA at 18 V and 25°C - 5-V, 10-V, and 15-V parametric ratings
- Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
CD4572UBPW Parameters
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