CD74ACT112 Datasheet - Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset

CD74ACT112 Description
Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
CD74ACT112 Vendor
Texas Instruments
CD74ACT112 Categories
Flip Flop
CD74ACT112 Features
Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
CD74ACT112 Datasheet and Application Notes
CD74ACT112 Datasheet
Parameter	Value
Voltage Nodes (V)
Products related to CD74ACT112
CD74ACT112M CD54ACT112F3A CD54ACT112 CD74ACT112M96

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