Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption
Digital Design Avoids Analog Compensation Errors
Easily Cascadable for Higher-Order Loops
Useful Frequency Range
- DC to 110 MHz Typical (K CLK)
- DC to 70 MHz Typical (I/D CLK)
Dynamically Variable Bandwidth
Very Narrow Bandwidth Attainable
Power-On Reset
Output Capability
- Standard: XORPD OUT, ECPD OUT
- Bus Driver: I/D OUT
SCR Latch-Up-Resistant CMOS Process and Circuit Design
Balanced Propagation Delays
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015

CD74ACT297M Parameters

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