- Edge-Triggered Data Flip-Flops
- Transparent Select Latches
- Buffered Inputs
- 3-State Complementary Outputs
- Bus Line Driving Capability
- Typical Propagation Delay: VCC= 5V, CL = 15pF, TA = 25°C
- Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
|