| CDC2509B Description |
| 1-to-9 PLL Clock Driver |
| CDC2509B Vendor |
| Texas Instruments |
| CDC2509B Categories |
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| CDC2509B Features |
- Use CDCVF2509A as a Replacement for this Device
- Designed to Meet PC SDRAM Registered DIMM Specification
- Spread Spectrum Clock Compatible
- Operating Frequency 25 MHz to 125 MHz
- Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps
- Jitter (peak - peak) at 66 MHz to 100 MHz Is ±80 ps
- Jitter (cycle - cycle) at 66 MHz to 100 MHz Is |100 ps|
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
- Separate Output Enable for Each Output Bank
- External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
- On-Chip Series Damping Resistors
- No External RC Network Required
- Operates at 3.3 V
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| CDC2509B Datasheet and Application Notes |
|
| Parameter | Value |
| Input Level | LVTTL |
| Output Level | TTL |
| VCC (V) | 3.3 |
| t(phase error) (Min) (ps) | -200 |
| t(phase error) (Max) (ps) | 200 |
| No. of Outputs | 9 |
| Operating Frequency Range (Min) (MHz) | 25 |
| Operating Frequency Range (Max) (MHz) | 125 |
| Absolute Jitter (cycle-to-cycle) (ps) | 100 |
| Pin/Package | 24TSSOP |
| Approx. 1KU Price (US$) | 2.15 |
| Products related to CDC2509B |
| CDC2509BPWR |