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CDC2509B

CDC2509B Description

1-to-9 PLL Clock Driver

CDC2509B Categories

Clock Drivers

CDC2509B Manufacturer

Texas Instruments

CDC2509B Datasheet (PDF)

CDC2509B Datasheet

CDC2509B Price & Availability


Check CDC2509B Price & Availability at Canics

CDC2509B Features

  • Use CDCVF2509A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Specification
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps
  • Jitter (peak - peak) at 66 MHz to 100 MHz Is ±80 ps
  • Jitter (cycle - cycle) at 66 MHz to 100 MHz Is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V

CDC2509B Parameters

Pin/Package24TSSOP
Approx. 1KU Price (US$)2.15
Input LevelLVTTL
Output LevelTTL
No. of Outputs9
VCC (V)3.3
t(phase error) (Min) (ps)-200
t(phase error) (Max) (ps)200
Operating Frequency Range (Min) (MHz)25
Operating Frequency Range (Max) (MHz)125
Absolute Jitter (cycle-to-cycle) (ps)100
Select parameters and click to see components with these parameters.

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Keywords
CDC2509B Data Sheet CDC2509B Spec CDC2509B Application Notes CDC2509B Distributor
CDC2509B Circuit CDC2509B Reference CDC2509B PDF CDC2509B RoHS