CDC2509BPWR

CDC2509BPWR Description

Use CDCVF2509A as a Replacement for this Device
Designed to Meet PC SDRAM Registered DIMM Specification
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 125 MHz
Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ą150 ps
Jitter (peak - peak) at 66 MHz to 100 MHz Is ą80 ps
Jitter (cycle - cycle) at 66 MHz to 100 MHz Is |100 ps|
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V

CDC2509BPWR Data Sheet	CDC2509BPWR Spec	CDC2509BPWR Application Notes	CDC2509BPWR Distributor
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