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CDC2510BPWR

CDC2510BPWR Description

CDC2510BPWR Description

CDC2510BPWR Description

CDC2510BPWR Categories

CDC2510BPWR Manufacturer

CDC2510BPWR Datasheet (PDF)

CDC2510BPWR Datasheet
CDC2510B
CDC2510BPWR Datasheet

CDC2510BPWR Price & Availability


Check CDC2510BPWR Price & Availability at Canics

CDC2510BPWR Features

  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Specification
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • tPhase Error Minus Jitter at 66 MHz to 100 MHz Is ±150 ps
  • Jitter (pk - pk) at 66 MHz to 100 MHz is ±80ps
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3-V

CDC2510BPWR Parameters

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Keywords
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CDC2510BPWR Circuit CDC2510BPWR Reference CDC2510BPWR PDF CDC2510BPWR RoHS