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CDC2516DGGR

CDC2516DGGR Description

CDC2516DGGR Description

CDC2516DGGR Categories

CDC2516DGGR Manufacturer

CDC2516DGGR Datasheet (PDF)

CDC2516DGGR Price & Availability


Check CDC2516DGGR Price & Availability at Canics

CDC2516DGGR Features

  • Use CDCVF2510A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to Four Banks of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series-Damping Resistors
  • No External RC Network Required Operates at 3.3-V VCC
  • Packaged in Plastic 48-Pin Thin Shrink Small-Outline Package

CDC2516DGGR Parameters

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