CDC2586PAH

CDC2586PAH Description

Low Output Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
Distributes One Clock Input to 12 Outputs
Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
No External RC Network Required
External Feedback (FBIN) Synchronizes the Outputs to the Clock Input
Application for Synchronous DRAM, High-Speed Microprocessor
TTL-Compatible Inputs and Outputs
Outputs Have Internal 26- Series Resistors to Dampen Transmission-Line Effects
State-of-the-Art EPIC-IIB? BiCMOS Design Significantly Reduces Power Dissipation
Distributed V_CC and Ground Pins Reduce Switching Noise
Packaged in 52-Pin Thin Quad Flat Package>

CDC2586PAH Data Sheet	CDC2586PAH Spec	CDC2586PAH Application Notes	CDC2586PAH Distributor
CDC2586PAH Circuit	CDC2586PAH Reference	CDC2586PAH PDF	CDC2586PAH RoHS