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CDC318A Datasheet (PDF)
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CDC318A Features- High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
- Output Skew, tsk(o), Less Than 250 ps
- Pulse Skew, tsk(p), Less Than 500 ps
- Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules (DIMMs)
- I2C Serial Interface Provides Individual Enable Control for Each Output
- Operates at 3.3 V
- Distributed VCC and Ground Pins Reduce Switching Noise
- 100-MHz Operation
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
- Packaged in 48-Pin Shrink Small Outline (DL) Package
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