CDC318ADLR

CDC318ADLR Description

High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications
Output Skew, t_sk(o), Less Than 250 ps
Pulse Skew, t_sk(p), Less Than 500 ps
Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules (DIMMs)
I²C Serial Interface Provides Individual Enable Control for Each Output
Operates at 3.3 V
Distributed V_CC and Ground Pins Reduce Switching Noise
100-MHz Operation
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Packaged in 48-Pin Shrink Small Outline (DL) Package

CDC318ADLR Data Sheet	CDC318ADLR Spec	CDC318ADLR Application Notes	CDC318ADLR Distributor
CDC318ADLR Circuit	CDC318ADLR Reference	CDC318ADLR PDF	CDC318ADLR RoHS