High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM (Synchronous DRAM) Clock Buffering Applications
Output Skew, t_sk(o), Less Than 250 ps
Pulse Skew, t_sk(p), Less Than 500 ps
Supports up to Two Unbuffered SDRAM DIMMs (Dual Inline Memory Modules)
I²C Serial Interface Provides Individual Enable Control for Each Output
Operates at 3.3 V
Distributed V_CC and Ground Pins Reduce Switching Noise
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
Packaged in 28-Pin Shrink Small Outline (DB) Package

CDC319DB Parameters

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