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CDC509PWR

CDC509PWR Description

CDC509PWR Description

CDC509PWR Categories

CDC509PWR Manufacturer

CDC509PWR Datasheet (PDF)

CDC509PWR Price & Availability


Check CDC509PWR Price & Availability at Canics

CDC509PWR Features

  • Use CDCVF2509A as a Replacement for this Device
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
  • Separate Output Enable for Each Output Bank
  • External Feedback (FBIN) Pin Is Used to Synchronize the Outputs to the Clock Input
  • No External RC Network Required
  • Operates at 3.3-V VCC
  • Packaged in Plastic 24-Pin Thin Shrink Small-Outline Package

CDC509PWR Parameters

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