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CDC536DB

CDC536DB Description

3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options

CDC536DB Description

IC 3.3V PLL CLOCK DRIVER 28-SSOP

CDC536DB Categories

Clock Drivers

CDC536DB Manufacturer

Texas Instruments

CDC536DB Datasheet (PDF)

CDC536DB Datasheet
CDC536
CDC536: 3.3-V PLL Clock Driver With 3-State Outputs (Rev. G)

CDC536DB Price & Availability


Check CDC536DB Price & Availability at Canics

CDC536DB Features

  • Low-Output Skew for Clock-Distribution and Clock-Generation Applications
  • Operates at 3.3-V VCC
  • Distributes One Clock Input to Six Outputs
  • One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency
  • No External RC Network Required
  • External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
  • Application for Synchronous DRAM, High-Speed Microprocessor
  • Negative-Edge-Triggered Clear for Half-Frequency Outputs
  • TTL-Compatible Inputs and Outputs
  • Outputs Drive 50- Parallel-Terminated Transmission Lines
  • State-of-the-Art EPIC-IIB? BiCMOS Design Significantly Reduces Power Dissipation
  • Distributed VCC and Ground Pins Reduce Switching Noise
  • Packaged in Plastic 28-Pin Shrink Small Outline Package

CDC536DB Parameters

Pin/Package28SSOP
Approx. 1KU Price (US$)2
StatusACTIVE
Budget Price ($US) | QTY2.00 | 1KU
Package Type | PinsSSOP (DB) | 28
STD Pack QTY50
TypeDriver, PLL
Input LevelTTL
Output LevelLVTTL
OutputLVTTL
Temp Range (C)0 to 70
CategoryIntegrated Circuits (ICs)
Phase Error+/-500
FamilyClock/Timing - Clock Buffers, Drivers
VCC (V)3.3
Multiplier Ratio1/2, 1, 2
Output Frequency (Min) (Mhz)25
Output Frequency (Max) (Mhz)100
Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)P-P 200ps
Output Skew (ps)500
InputTTL
Operating Temperature0°C ~ 70°C
Package / Case28-SSOP
Number of Circuits*
Voltage - Supply3 V ~ 3.6 V
Frequency-Max100MHz
Ratio - Input:Output*
Differential - Input:Output*
Select parameters and click to see components with these parameters.

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Keywords
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