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CDC586 Datasheet (PDF)
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CDC586 Features- Low Output Skew for Clock-Distribution and Clock-Generation Applications
- Operates at 3.3-V VCC
- Distributes One Clock Input to Twelve Outputs
- Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency
- No External RC Network Required
- External Feedback Pin (FBIN) Is Used to Synchronize the Outputs to the Clock Input
- Application for Synchronous DRAM, High-Speed Microprocessor
- TTL-Compatible Inputs and Outputs
- Outputs Drive Parallel 50- Terminated Transmission Lines
- State-of-the-Art EPIC-IIB? BiCMOS Design Significantly Reduces Power Dissipation
- Distributed VCC and Ground Pins Reduce Switching Noise
- Packaged in 52-Pin Thin Quad Flat Package
CDC586 Parameters
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