Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications
Distributes One Differential Clock Input to Ten Differential Outputs
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Clock Input
Operates at V_CC = 2.5 V and AV_CC = 3.3 V
Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outline Package (TSSOP)
Spread Spectrum Clocking Tracking Capability to Reduce EMI

CDC857-2DGGR Parameters

Products Similar to CDC857-2DGGR

CDC857-2DGGR Data Sheet	CDC857-2DGGR Spec	CDC857-2DGGR Application Notes	CDC857-2DGGR Distributor
CDC857-2DGGR Circuit	CDC857-2DGGR Reference	CDC857-2DGGR PDF	CDC857-2DGGR RoHS