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CDC857 Datasheet (PDF)
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CDC857 Features- Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications
- Distributes One Differential Clock Input to Ten Differential Outputs
- External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Clock Input
- Operates at VCC = 2.5 V and AVCC = 3.3 V
- Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outline Package (TSSOP)
- Spread Spectrum Clocking Tracking Capability to Reduce EMI
CDC857 Parameters
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