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CDC857

CDC857 Description

CDC857 Description

CDC857 Categories

CDC857 Manufacturer

CDC857 Datasheet (PDF)

CDC857 Price & Availability


Check CDC857 Price & Availability at Canics

CDC857 Features

  • Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Clock Input
  • Operates at VCC = 2.5 V and AVCC = 3.3 V
  • Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outline Package (TSSOP)
  • Spread Spectrum Clocking Tracking Capability to Reduce EMI

CDC857 Parameters

StatusACTIVE
Budget Price ($US) | QTY6.65 | 1KU
Package Type | PinsTSSOP (DGG) | 48
STD Pack QTY40
Select parameters and click to see components with these parameters.

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Keywords
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