CDCF2509PW

CDCF2509PW Description

Use CDCVF2509A as a Replacement for this Device
Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 140 MHz
Static Phase Error Distribution at 66 MHz to 133 MHz is Б125 ps
Jitter (cyc-cyc) at 66 MHz to 133 MHz Is |70| ps
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs
Separate Output Enable for Each Output Bank
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V

CDCF2509PW Data Sheet	CDCF2509PW Spec	CDCF2509PW Application Notes	CDCF2509PW Distributor
CDCF2509PW Circuit	CDCF2509PW Reference	CDCF2509PW PDF	CDCF2509PW RoHS