CDCF2510PW

CDCF2510PW Description

Use CDCVF2510A as a Replacement for this Device
Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9
Spread Spectrum Clock Compatible
Operating Frequency 25 MHz to 140 MHz
Static Phase Error Distribution at 66 MHz to 133 MHz is ą125 ps
Jitter (cyc-cyc) at 66 MHz to 133 MHz Is |70| ps
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
Distributes One Clock Input to One Bank of Ten Outputs
Output Enable Pin to Enable/Disable All 10 Outputs
External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V

CDCF2510PW Data Sheet	CDCF2510PW Spec	CDCF2510PW Application Notes	CDCF2510PW Distributor
CDCF2510PW Circuit	CDCF2510PW Reference	CDCF2510PW PDF	CDCF2510PW RoHS