CDCU877

CDCU877 Description

1.8V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 10 MHz to 400 MHz
Low Current Consumption: <135 mA
Low Jitter (Cycle-Cycle): ±30 ps
Low Output Skew: 35ps
Low Period Jitter: ±20 ps
Low Dynamic Phase Offset: ±15 ps
Low Static Phase Offset: ±50 ps
Distributes One Differential Clock Input to Ten Differential Outputs
52-ball µBGA (MicroStar Junior? BGA, 0,65mm pitch) and 40-pin MLF
External Feedback Pins (FBIN, FBIN\) are Used to Synchronize the Outputs to the Input Clocks
Single-Ended Input and Single-Ended Output Modes
Meets or Exceeds JEDEC82-8 PLL Standard for PC2-3200/4200
Fail-Safe Inputs

CDCU877 Data Sheet	CDCU877 Spec	CDCU877 Application Notes	CDCU877 Distributor
CDCU877 Circuit	CDCU877 Reference	CDCU877 PDF	CDCU877 RoHS