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CDCU877AZQLT Datasheet (PDF)
CDCU877AZQLT Price & Availability
CDCU877AZQLT Features- 1.8V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications
- Spread Spectrum Clock Compatible
- Operating Frequency: 10 MHz to 400 MHz
- Low Current Consumption: <135 mA
- Low Jitter (Cycle-Cycle): ±30 ps
- Low Output Skew: 35ps
- Low Period Jitter: ±20 ps
- Low Dynamic Phase Offset: ±15 ps
- Low Static Phase Offset: ±50 ps
- Distributes One Differential Clock Input to Ten Differential Outputs
- 52-ball µBGA (MicroStar Junior? BGA, 0,65mm pitch) and 40-pin MLF
- External Feedback Pins (FBIN, FBIN\) are Used to Synchronize the Outputs to the Input Clocks
- Single-Ended Input and Single-Ended Output Modes
- Meets or Exceeds JEDEC82-8 PLL Standard for PC2-3200/4200
- Fail-Safe Inputs
CDCU877AZQLT Parameters
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