CDCV850DGG

CDCV850DGG Description

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 140 MHz
Low Jitter (cyc-cyc): ±75 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Two-Line Serial Interface Provides Output Enable and Functional Control
Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz
48-Pin TSSOP Package
Consumes <250-µA Quiescent Current
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV850DGG Data Sheet	CDCV850DGG Spec	CDCV850DGG Application Notes	CDCV850DGG Distributor
CDCV850DGG Circuit	CDCV850DGG Reference	CDCV850DGG PDF	CDCV850DGG RoHS