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CDCV850IDGG

CDCV850IDGG Description

2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface

CDCV850IDGG Description

IC PLL CLOCK DRVR 2.5V 48-TSSOP

CDCV850IDGG Categories

Clock Drivers

CDCV850IDGG Manufacturer

Texas Instruments

CDCV850IDGG Datasheet (PDF)

CDCV850IDGG Datasheet
CDCV850(I)
2.5-V Phase Lock Loop Clock Driver With 2-Line Serial Interface (Rev. B)

CDCV850IDGG Price & Availability


Check CDCV850IDGG Price & Availability at Canics

CDCV850IDGG Features

  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 to 140 MHz
  • Low Jitter (cyc-cyc): ±75 ps
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • Two-Line Serial Interface Provides Output Enable and Functional Control
  • Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz
  • 48-Pin TSSOP Package
  • Consumes <250-µA Quiescent Current
  • External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV850IDGG Parameters

Pin/Package48TSSOP
Approx. 1KU Price (US$)1.55
StatusACTIVE
Temp (oC)-40 to 85
Budget Price ($US) | QTY1.80 | 1KU
Package Type | PinsTSSOP (DGG) | 48
STD Pack QTY40
TypePLL Clock Driver
Input LevelSSTL-2, LVTTL
Output LevelSSTL-2
OutputSSTL-2
No. of Outputs10
CategoryIntegrated Circuits (ICs)
FamilyClock Buffers, Drivers
VCC (V)2.5
t(phase error) (Min) (ps)-120
t(phase error) (Max) (ps)120
Operating Frequency Range (Min) (MHz)60
Operating Frequency Range (Max) (MHz)140
Absolute Jitter (cycle-to-cycle) (ps)30
InputLVTTL, SSTL-2
Operating Temperature-40°C ~ 85°C
Number of Outputs10
Package / Case48-TSSOP
Voltage - Supply2.375 V ~ 2.625 V
Frequency-Max140MHz
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