CDCV850IDGGR

CDCV850IDGGR Description

Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 to 140 MHz
Low Jitter (cyc-cyc): ±75 ps
Distributes One Differential Clock Input to Ten Differential Outputs
Two-Line Serial Interface Provides Output Enable and Functional Control
Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are <20 MHz
48-Pin TSSOP Package
Consumes <250-µA Quiescent Current
External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

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