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CDCV855

CDCV855 Description

1:4 DDR PLL Clock Driver

CDCV855 Categories

Clock Drivers

CDCV855 Manufacturer

Texas Instruments

CDCV855 Datasheet (PDF)

CDCV855 Datasheet
2.5-V Phase-Lock Loop Clock Driver (Rev. A)

CDCV855 Price & Availability


Check CDCV855 Price & Availability at Canics

CDCV855 Features

  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 180 MHz
  • Low Jitter (cyc-cyc): ±50 ps
  • Distributes One Differential Clock Input to Four Differential Clock Outputs
  • Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
  • Operates From Dual 2.5-V Supplies
  • 28-Pin TSSOP Package
  • Consumes < 200-µA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV855 Parameters

Pin/Package28TSSOP
Approx. 1KU Price (US$)1.15
Input LevelSSTL-2
Output LevelSSTL-2
No. of Outputs4
VCC (V)2.5
t(phase error) (Min) (ps)-100
t(phase error) (Max) (ps)100
Operating Frequency Range (Min) (MHz)60
Operating Frequency Range (Max) (MHz)180
Absolute Jitter (cycle-to-cycle) (ps)50
Select parameters and click to see components with these parameters.

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Keywords
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