Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 180 MHz
Low Jitter (cyc-cyc): ±50 ps
Distributes One Differential Clock Input to Four Differential Clock Outputs
Enters Low Power Mode and Three-State Outputs When Input CLK Signal Is Less Than 20 MHz or PWRDWN Is Low
Operates From Dual 2.5-V Supplies
28-Pin TSSOP Package
Consumes < 200-µA Quiescent Current
External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV855IPWR Parameters

Products Similar to CDCV855IPWR

CDCV855IPWR Data Sheet	CDCV855IPWR Spec	CDCV855IPWR Application Notes	CDCV855IPWR Distributor
CDCV855IPWR Circuit	CDCV855IPWR Reference	CDCV855IPWR PDF	CDCV855IPWR RoHS