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CDCV857ADGG

CDCV857ADGG Description

2.5V SSTL-II Phase Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications

CDCV857ADGG Description

IC SSTL-II PLL CLK-DRVR 48-TSSOP

CDCV857ADGG Categories

Clock Drivers

CDCV857ADGG Manufacturer

Texas Instruments

CDCV857ADGG Datasheet (PDF)

CDCV857ADGG Datasheet
CDCV857A
2.5-V Phase Lock Loop Clock Driver (Rev. A)

CDCV857ADGG Price & Availability


Check CDCV857ADGG Price & Availability at Canics

CDCV857ADGG Features

  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 to 180 MHz
  • Low Jitter (cyc-cyc): ±50 ps
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • Three-State Outputs When the Input Differential Clocks Are <20 MHz
  • Operates From Dual 2.5-V Supplies
  • Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior? BGA Package
  • Consumes < 200-uA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857ADGG Parameters

Pin/Package48TSSOP,56BGA MICROSTAR JUNIOR
Approx. 1KU Price (US$)2.5
StatusACTIVE
Temp (oC)0 to 85
Budget Price ($US) | QTY2.50 | 1KU
Package Type | PinsTSSOP (DGG) | 48
STD Pack QTY40
TypeDriver, PLL
Input LevelSSTL-2
Output LevelSSTL-2
OutputSSTL-2
No. of Outputs10
CategoryIntegrated Circuits (ICs)
FamilyClock/Timing - Clock Buffers, Drivers
VCC (V)2.5
t(phase error) (Min) (ps)100
t(phase error) (Max) (ps)100
Operating Frequency Range (Min) (MHz)60
Operating Frequency Range (Max) (MHz)180
Absolute Jitter (cycle-to-cycle) (ps)50
InputSSTL-2
Operating Temperature0°C ~ 85°C
Package / Case48-TSSOP
Number of Circuits*
Voltage - Supply2.375 V ~ 2.625 V
Frequency-Max200MHz
Ratio - Input:Output*
Differential - Input:Output*
Select parameters and click to see components with these parameters.

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Keywords
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