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CDCV857AGQLR

CDCV857AGQLR Description

CDCV857AGQLR Description

CDCV857AGQLR Description

CDCV857AGQLR Description

CDCV857AGQLR Categories

CDCV857AGQLR Manufacturer

CDCV857AGQLR Datasheet (PDF)

CDCV857AGQLR Price & Availability


Check CDCV857AGQLR Price & Availability at Canics

CDCV857AGQLR Features

  • Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 to 180 MHz
  • Low Jitter (cyc-cyc): ±50 ps
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • Three-State Outputs When the Input Differential Clocks Are <20 MHz
  • Operates From Dual 2.5-V Supplies
  • Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior? BGA Package
  • Consumes < 200-uA Quiescent Current
  • External Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks

CDCV857AGQLR Parameters

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