CDCV857BIDGGR DescriptionCDCV857BIDGGR DescriptionCDCV857BIDGGR DescriptionCDCV857BIDGGR CategoriesCDCV857BIDGGR Manufacturer
CDCV857BIDGGR Datasheet (PDF)
CDCV857BIDGGR Price & Availability
CDCV857BIDGGR Features- Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications
- Spread Spectrum Clock Compatible
- Operating Frequency: 60 MHz to 200 MHz
- Low Jitter (cycle-cycle): ±50 ps
- Low Static Phase Offset: ±50 ps
- Low Jitter (Period): ±35 ps
- Distributes One Differential Clock Input to 10 Differential Outputs
- Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low
- Operates From Dual 2.5-V Supplies
- Available in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior? BGA Package
- Consumes < 100-µA Quiescent Current
- External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
- Meets/Exceeds the Latest DDR JEDEC Spec JESD82-1
CDCV857BIDGGR Parameters
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