Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-cycle): <|150 ps| Over the Range 66 MHz.200 MHz
Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay)
Three-States Outputs When There Is no Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC Packages
Consumes Less Than 100-uA (Typically) in Power Down Mode
Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
25- On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the Need for External Components

CDCVF2505D Parameters

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