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CDCVF2505DR

CDCVF2505DR Description

PLL Clock Driver for Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode

CDCVF2505DR Description

IC 3.3V PLL CLOCK DRVR 8-SOIC

CDCVF2505DR Categories

Clock Drivers

CDCVF2505DR Manufacturer

Texas Instruments

CDCVF2505DR Datasheet (PDF)

CDCVF2505DR Datasheet
CDCVF2505
3.3-V Clock Phase Lock-Loop Clock Driver (Rev. E)

CDCVF2505DR Price & Availability


Check CDCVF2505DR Price & Availability at Canics

CDCVF2505DR Features

  • Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 24 MHz to 200 MHz
  • Low Jitter (Cycle-cycle): <|150 ps| Over the Range 66 MHz.200 MHz
  • Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay)
  • Three-States Outputs When There Is no Input Clock
  • Operates From Single 3.3-V Supply
  • Available in 8-Pin TSSOP and 8-Pin SOIC Packages
  • Consumes Less Than 100-uA (Typically) in Power Down Mode
  • Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
  • 25- On-Chip Series Damping Resistors
  • Integrated RC PLL Loop Filter Eliminates the Need for External Components

CDCVF2505DR Parameters

Pin/Package8SOIC,8TSSOP
Approx. 1KU Price (US$).75
StatusACTIVE
Temp (oC)-40 to 85
Budget Price ($US) | QTY0.75 | 1KU
Package Type | PinsSOIC (D) | 8
STD Pack QTY2500
TypePLL Clock Driver
Input LevelLVTTL
Output LevelLVTTL
OutputLVTTL
No. of Outputs5
CategoryIntegrated Circuits (ICs)
FamilyClock Buffers, Drivers
FamilyClock/Timing - Clock Generators, PLLs, Frequency Synthesizers
VCC (V)3.3
Operating Frequency Range (Min) (MHz)24
Operating Frequency Range (Max) (MHz)200
Absolute Jitter (cycle-to-cycle) (ps)150
InputLVTTL
Operating Temperature-40°C ~ 85°C
Number of Outputs5
Package / Case8-SOIC (3.9mm Width)
Voltage - Supply3 V ~ 3.6 V
Frequency-Max200MHz
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Keywords
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