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CDCVF2510

CDCVF2510 Description

3.3-V Phase-Lock Loop Clock Driver

CDCVF2510 Categories

Clock Drivers

CDCVF2510 Manufacturer

Texas Instruments

CDCVF2510 Datasheet (PDF)

CDCVF2510 Datasheet
3.3-V Phase-Lock Loop Clock Driver (Rev. C)

CDCVF2510 Price & Availability


Check CDCVF2510 Price & Availability at Canics

CDCVF2510 Features

  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
  • Spread Spectrum Clock Compatible
  • Operating Frequency 50 MHz to 175 MHz
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
  • Jitter (cyc ? cyc) at 66 MHz to 166 MHz Is |70| ps
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • 25- On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V

CDCVF2510 Parameters

Pin/Package24TSSOP
Approx. 1KU Price (US$)2.25
Input LevelLVTTL
Output LevelLVTTL
No. of Outputs10
VCC (V)3.3
t(phase error) (Min) (ps)-50
t(phase error) (Max) (ps)50
Operating Frequency Range (Min) (MHz)66
Operating Frequency Range (Max) (MHz)175
Absolute Jitter (cycle-to-cycle) (ps)75
Select parameters and click to see components with these parameters.

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