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CDCVF2510A

CDCVF2510A Description

3.3-V Phase-Lock Loop Clock Driver with Power Down Mode

CDCVF2510A Categories

Clock Drivers

CDCVF2510A Manufacturer

Texas Instruments

CDCVF2510A Datasheet (PDF)

CDCVF2510A Datasheet
3.3-V Phase-Lock Loop Clock Driver (Rev. C)

CDCVF2510A Price & Availability


Check CDCVF2510A Price & Availability at Canics

CDCVF2510A Features

  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
  • Spread Spectrum Clock Compatible
  • Operating Frequency 20 MHz to 175 MHz
  • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps
  • Jitter (cyc - cyc) at 66 MHz to 166 MHz is |70| ps
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices
  • Auto Frequency Detection to Disable Device (Power-Down Mode)
  • Available in Plastic 24-Pin TSSOP
  • Distributes One Clock Input to One Bank of 10 Outputs
  • External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input
  • 25- On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • applications
    • DRAM Applications
    • PLL Based Clock Distributors
    • Non-PLL Clock Buffer

CDCVF2510A Parameters

Pin/Package24TSSOP
Approx. 1KU Price (US$)2.25
Input LevelLVTTL
Output LevelLVTTL
No. of Outputs10
VCC (V)3.3
t(phase error) (Min) (ps)-50
t(phase error) (Max) (ps)50
Operating Frequency Range (Min) (MHz)66
Operating Frequency Range (Max) (MHz)175
Absolute Jitter (cycle-to-cycle) (ps)75
Select parameters and click to see components with these parameters.

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Keywords
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