Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
Spread Spectrum Clock Compatible
Operating Frequency 20 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to 166 MHz is Б125 ps
Jitter (cyc - cyc) at 66 MHz to 166 MHz is |70| ps
Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices
Auto Frequency Detection to Disable Device (Power-Down Mode)
Available in Plastic 24-Pin TSSOP
Distributes One Clock Input to One Bank of 10 Outputs
External Feedback (FBIN) Terminal is Used to Synchronize the Outputs to the Clock Input
25- On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
applications
- DRAM Applications
- PLL Based Clock Distributors
- Non-PLL Clock Buffer

CDCVF2510APW Parameters

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