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CDCVF2510PW Datasheet (PDF)
CDCVF2510PW Price & Availability
CDCVF2510PW Features- Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
- Spread Spectrum Clock Compatible
- Operating Frequency 50 MHz to 175 MHz
- Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
- Jitter (cyc ? cyc) at 66 MHz to 166 MHz Is |70| ps
- Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices
- Available in Plastic 24-Pin TSSOP
- Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
- Distributes One Clock Input to One Bank of Ten Outputs
- External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
- 25- On-Chip Series Damping Resistors
- No External RC Network Required
- Operates at 3.3 V
CDCVF2510PW Parameters
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