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CDCVF857

CDCVF857 Description

2.5 V Phase Lock Loop DDR Clock Driver

CDCVF857 Categories

Clock Drivers

CDCVF857 Manufacturer

Texas Instruments

CDCVF857 Datasheet (PDF)

CDCVF857 Datasheet
2.5V Phase-Lock Loop Clock Driver (Rev. F)

CDCVF857 Price & Availability


Check CDCVF857 Price & Availability at Canics

CDCVF857 Features

  • Recommended Applications:
    • DDR Memory Modules (DDR400/333/266/200)
    • Zero Delay Fan-Out Buffer
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 220 MHz
  • Low Jitter (Cycle-Cycle): ±35 ps
  • Low Static Phase Offset: ±50 ps
  • Low Jitter (Period): ±30 ps
  • 1 To 10 Differential Clock Distribution (SSTL2)
  • Best in Class for VOX = VDD/2 ±0.1 V
  • Operates From Dual 2.6-V Supplies or 2.5-V Supplies
  • Available in a 40-Pin MLF Package, 48-Pin TSSOP Package, 56-Ball MicroStar Junior? BGA Package
  • Consumes < 100-µA Quiescent Current
  • External Feedback Pins (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input Clocks
  • Meets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 Specification
  • Meets/Exceeds Proposed DDRI-400 Spec (JESD82-1A)
  • Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low

CDCVF857 Parameters

Pin/Package40QFN,48TSSOP,56BGA MICROSTAR JUNIOR
Approx. 1KU Price (US$)3.15
Input LevelSSTL-2
Output LevelSSTL-2
No. of Outputs10
VCC (V)2.3 to 2.7
t(phase error) (Min) (ps)-50
t(phase error) (Max) (ps)50
Operating Frequency Range (Min) (MHz)60
Operating Frequency Range (Max) (MHz)220
Absolute Jitter (cycle-to-cycle) (ps)50
Select parameters and click to see components with these parameters.

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