| DAC5674IPHP Description |
| 14-Bit, 400 CommsDAC, 2x/4x Interpolation Filters |
| DAC5674IPHP Vendor |
| Texas Instruments |
| DAC5674IPHP Features |
- 200-MSPS Maximum Input Data Rate
- 400-MSPS Maximum Update Rate DAC
- 76-dBc SFDR Over Full First Nyquist Zone With Single Tone Input Signal (Fout = 21 MHz)
- 74-dBc ACPR W-CDMA at 15.36 MHz IF
- 69-dBc ACPR W-CDMA at 30.72 MHz IF
- Selectable 2x or 4x Interpolation Filter
- Linear Phase
- 0.05-dB Passband Ripple
- 80-dB Stopband Attenuation
- Stopband Transition 0.4-0.6 Fdata
- nterpolation Filters Configurable in Either Low-Pass or High-Pass Mode, Allows For Selection Higher Order Image
- On-chip 2x/4x PLL Clock Multiplier, PLL Bypass Mode
- Differential Scalable Current Outputs: 2 mA to 20 mA
- On-Chip 1.2-V Reference
- 1.8-V Digital and 3.3-V Analog Supply Operation
- 1.8/3.3-V CMOS Compatible Interface
- Power Dissipation: 435 mW at 400 MSPS
- Package: 48-Pin TQFP
- APPLICATIONS
- Cellular Base Transceiver Station Transmit Channel
- CDMA: W-CDMA, CDMA2000, IS-95
- TDMA: GSM, IS-136, EDGE/UWC-136
- Test and Measurement: Arbitrary Waveform Generation
- Direct Digital Synthesis (DDS)
- Cable Modem Termination System
|
| DAC5674IPHP Datasheet and Application Notes |
|
| Parameter | Value |
| Resolution (Bits) | 14 |
| Settling Time (us) | 0.02 |
| Update Rate (MSPS) | 400 |
| Power Consumption (Typ) (mW) | 435 |
| Output Type | Current |
| Current Range (mA) | 20 |
| Architecture | I-steering |
| DAC: Channels | 1 |
| Analog Voltage AV/DD (Min) (V) | 3 |
| Analog Voltage AV/DD (Max) (V) | 3.6 |
| Logic Voltage DV/DD (Min) (V) | 1.65 |
| Logic Voltage DV/DD (Max) (V) | 1.95 |
| DNL (Max) (+/-LSB) | 2 |
| INL (Max) (+/-LSB) | 3.5 |
| SNR (Typ) (dB) | 71 |
| SFDR (Typ) (dB) | 76 |
| Pin/Package | 48HTQFP |
| Approx. 1KU Price (US$) | 19 |
| Status | ACTIVE |
| Temp (oC) | -40 to 85 |
| Budget Price ($US) | QTY | 19.00 | 1KU |
| Package Type | Pins | HTQFP (PHP) | 48 |
| STD Pack QTY | 250 |
| Products related to DAC5674IPHP |
| DAC5674 DAC5674IPHPR |