| SM32C6416DGLZ50AEP Description |
| EP - Military Enhanced Plastic Fixed-Point Digital Signal Processor |
| SM32C6416DGLZ50AEP Vendor |
| Texas Instruments |
| SM32C6416DGLZ50AEP Features |
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of –40°C to 105°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
- 2-ns Instruction Cycle Time
- 500-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4000 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions With 6 ALUs and 2 Multipliers
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
- Viterbi Decoder Coprocessor (VCP) [C6416]
- Supports Over 500 7.95-Kbps AMR
- Programmable Code Parameters
- Turbo Decoder Coprocessor (TCP) [C6416]
- Supports up to Six 2-Mbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
- L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache
- 128K-Bit (16K-Byte) L1D Data Cache
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache
- Two External Memory Interfaces (EMIFs) for 1280M-Byte Addressable External Memory
- Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
- Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
- 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416]
- Three PCI Bus Address Registers
- Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
- Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
- Three 32-Bit General-Purpose Timers
- Universal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
- Sixteen General-Purpose I/O (GPIO) Pins
- Flexible PLL Clock Generator
- IEEE-1149.1 (JTAGBoundary-Scan-Compatible
- 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
- 0.13-µm/6-Level Metal Process (CMOS)
- 3.3-V I/Os, 1.25-V Internal (500 MHz)
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| SM32C6416DGLZ50AEP Datasheet and Application Notes |
|
| Parameter | Value |
| Status | ACTIVE |
| Temp (oC) | -40 to 105 |
| Budget Price ($US) | QTY | 228.88 | 1KU |
| Package Type| Pins | FCBGA (GLZ) | 532 |
| STD Pack QTY | 1 |
| Products related to SM32C6416DGLZ50AEP |
SM320C6414 SM320C6415DGADW60 SM320C6415 SM320C6416
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