TLK3104SA

TLK3104SA Description

Quad 3.125 Gbps per Channel Transceiver Providing 10 Gbps Data Throughput
Selectable Synchronized or Independent Channel Operation
Selectable Transmitter Only, Receiver Only, or Transceiver Functions
Selectable On-Chip 8-Bit/10-Bit Encoding/Decoding (ENDEC)
Supports IEEE 802.3ae Proposed XGMII Parallel Interface
Supports IEEE 802.3ae Proposed XAUI Serial Interface
Receiver Differential Input Thresholds 200-mV
On-Chip 100- Differential Receiver Termination
No External Filter Capacitors Required
PECL-Compatible Differential Signaling Serial Interface Using Voltage Mode Logic (VML) Driver
Auto-Selects Between 1.8-V HSTL or SSTL_2 Class 1 I/O With On-Chip 50- Series Termination on Outputs
Able to Operate With a Single 2.5-V Power Supply
On-Chip Pseudo-Random Bit Stream (PRBS) Generation and Verification for Self-Test
IEEE 802.3 Management Data Input/Output (MDIO) Interface
IEEE 1149.1 JTAG Test Interface
Hot Plug Protection
Mainstream 250 nm CMOS Technology
Small Footprint 19×19 mm 289 Ball PBGA Package

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