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P610ARM-B

P610ARM-B Manufacturer

P610ARM-B Description

P610ARM-B Categories

P610ARM-B Datasheet (PDF)

P610ARM-B Datasheet

P610ARM-B Price & Availability


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P610ARM-B Features

  • High performance RISC - 25 MIPS sustained at 33 MHz (33 MIPS peak)
  • Fast sub microsecond interrupt response for real-time applications
  • Memory Management Unit (MMU) support for virtual memory systems
  • Excellent high-level language support
  • 4 kB of instruction & data cache
  • Big and Little Endian operating modes
  • Write Buffer - enhancing performance
  • IEEE 1149.1 Boundary Scan
  • Fully static operation, low power consumption - ideal for power sensitive applications
  • 144 Thin Quad Flat Pack (TQFP) package

P610ARM-B Description

    The P610ARM-B is a general purpose 32-bit microprocessor with 4 kB cache, write buffer and Memory Management Unit (MMU) combined in a single chip. The P610ARM offers high level RISC performance yet its fully static design ensures minimal power consumption, making it ideal for portable, low-cost systems.

    The innovative MMU supports a conventional two-level page-table structure and a number of extensions which make it ideal for embedded control, UNIX and Object Oriented systems. This results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.

     

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