PDSP16256/A

Zarlink Semiconductor

PDSP16256/A Datasheet

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The PDSP16256 contains sixteen multiplier - accumulators, which can be multi-cycled to provide from 16 to 128 stages of digital filtering. Input data and coefficients are both represented by 16-bit two's complement numbers with coefficients converted internally to 12 bits and the results being accumulated up to 32 bits.

In 16-tap mode the device samples data at the system clock rate of up to 25 MHz. If a lower sample rate is acceptable then the number of stages can be increased in powers of two up to a maximum of 128. Each time the number of stages is doubled, the sample clock rate must be halved with respect to the system clock. With 128 stages the sample clock is therefore one eighth of the system clock.

In all speed modes devices can be cascaded to provide filters of any length, only limited by the possibility of accumulator overflow. The 32-bit results are passed between cascaded devices without any intermediate scaling and subsequent loss of precision.